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Digital Summation

Developments in TDI CMOS Sensor Architectures

The high-volume mobile device market has played a significant role in driving CMOS image sensor innovation, resulting in less expensive, higher resolution and faster CMOS sensors. Because of this, CMOS-based imaging products are generally cheaper to manufacture than those built around CCD technology. In addition, they allow for higher data rates, lower power, and lower read noise because of their ability to process signals in parallel, rather than serially.

Various line scan technologies. To achieve high responsivity, TDI uses multiple stages to capture multiple exposures. In these stages,
photogenerated signal charges are transferred in sync with object motion. Dual line scans are considered two-stage TDIs. (Bild: Teledyne Dalsa Inc.)

However, CCD still holds a place in machine vision, and primarily because of a technology known as Time Delay and Integration (TDI). TDI is a method of line scanning which provides dramatically increased responsivity compared to other video scanning methods. TDI is based on the concept of accumulating multiple exposures of the same (moving) object, effectively increasing the integration time available to collect incident light. The object motion must be synchronized with the exposures to ensure a crisp image. CCD-based TDI imagers have been available for many years, and while sensor manufacturers have been working hard to develop TDI for CMOS imagers, there are still challenges to overcome. Engineering TDI imagers with conventional CMOS Image Sensor (CIS) processes has been difficult because the signal must be read out of individual pixels as voltages. While companies began touting CMOS-based TDI as long as fifteen years ago, actual products are rare. However, demand for this technology is clearly there, so despite daunting engineering challenges, several solutions exist, and other solutions are on the way. Where these solutions differ is in how signal summation happens.

Signal summation

In CCD-based TDI solutions, signal summation happens in the charge domain within the pixel array, which has a lot of advantages in terms of high scanning speeds in light-starved applications, good contrast and uniformity, and other factors. However, CMOS sensors built with conventional CIS processes cannot do signal summation in the pixel array. CMOS-based TDI solutions get around this by summing in the voltage domain (analog or digital) off the pixel array, in a memory array that has an identical number of memory elements to the number of pixels. The memory can be implemented in either the analog domain or the digital domain, and either on- or off-chip. In all these cases, the signal level is read out directly from each pixel as voltage. Because summation takes place external to the pixel array, each and every pixel in the array must be read out each and every line time. With a given number of pixel rows, the same number of read operations has to be performed to obtain a summed row. This increases the read noise. It also requires faster processing circuitry since all pixel rows must be read and accumulate each and every line time. There can be significant penalties compared to a charge-based system, where the result is acquired with only one read operation per pixel column. Also, because these solutions require a memory array that has as many elements as the pixel array, additional space and power are required.

Charge summing for CMOS

Charge-based summing of multiple pixel rows has typically been based in CCD technology. It is the only technology where it has been possible to physically move charge between adjacent pixels. This is changing, as some of the process blocks common in CCD, like buried channel pixel structures, are being migrated to CIS processes. This makes charge summing possible on a CMOS substrate, albeit with the constraint of lower clock voltages which necessarily restrict charge handling capacity. These constraints show up as limitations in maximum signal size, and therefore as limitations in dynamic range. However, the lower read noise levels achievable with CMOS readouts versus CCD, as well as lower power dissipation and higher data output rates, make this a compelling technology choice for many applications. While this technology is still in its infancy, it offers promise for future product development.

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