Easy Interfaces
Reduce Time to Market with Transport Layer IP Cores
Several months of work by protocol engineers is typically required to design an interface for a vision system. A number of vision camera manufactures, such as Ozray, Crevis and Sick, are addressing this challenge by purchasing transport layer interfaces in the form of intellectual property (IP), which is provided ready to incorporate into FPGAs along with other camera features.
Image 1 | IP cores secure the interoperability of the camera and host while ensuring compliance with the latest version of the interface layer. Sensor to Image’s Vision Standard IP Cores solutions are delivered as a working reference design along with FPGA IP cores. (Bild: Euresys s.a.)
A decade ago, Camera Link was the most widely used machine vision transport layer interface. The streaming part of Camera Link was well defined, but the control path was not specified, so every camera implemented its own configuration protocol, requiring individual tweaks on host side to fully support the camera. Fast forward to today and machine vision communications between the camera and host computer has been largely standardized, primarily using CoaXPress, GigE and USB interfaces. The new vision standards are more complex and require tighter timing margins than earlier generations. Further complications are provided by the fact that the standards themselves are evolving, requiring review of the standard and sometimes an upgrade of the transport layer implementation. The emergence of machine vision transport layer IP cores reduces the time required to develop camera-host interfaces. For example, Sensor to Image (S2I), a unit of Euresys, provides IP cores that meet the latest CXP, GigE Vision and USB3 Vision interface standards. These IP cores secure the interoperability of the camera and host while ensuring compliance with the latest version of the interface layer. S2I’s Vision Standard IP Cores solutions are delivered as a working reference design along with FPGA IP cores that have been fully tested against a wide range of popular frame grabbers and image acquisition libraries. The IP cores are compact, leaving plenty of room for additional vision functionality. They are compatible with Xilinx 7 and newer and Intel/Altera Cyclone V and more recent devices. The top-level design, consisting of the interface between external hardware such as the image sensor and transport layer PHY, is delivered as VHDL source code that can be adapted to custom hardware beyond the leading FPGA platforms supported by IP cores. The Video Acquisition Module of the reference design simulates a camera with a test pattern generator. This module is delivered as VHDL source code which is replaced by a sensor interface and pixel processing logic in the camera design. An FPGA integrated CPU (either MicroBlaze, NIOS or ARM) is used for several non-time-critical control and configuration tasks on the Vision Standard IP Cores. This software is written in C and can be extended by the customer. S2I has recently introduced an IMX Pregius IP core providing an interface to Sony Pregius Sub-LVDS image sensors. The company will also soon introduce an interface to MIPI sensors primarily used in embedded vision systems and mobile devices. The company offers a volume license best suited for companies with a large product line as well as a single-piece license which is the best option for companies with smaller lines.
