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Super FPGA

Heterogeneous Acceleration Platform for AI Applications

Xilinx introduced a new platform called ACAP (Adaptive Compute Acceleration Platform). inVISION magazine talked with Kirk Saban, Vice President, Product & Technical Marketing at Xilinx, about the advantages of the new platform and the first product series Versal.

A Versal ACAP (Adaptive Compute Acceleration Platform) is significantly different than a regular FPGA or SoC. Zero hardware ­expertise is required to boot the device. (Bild: Xilinx Ltd.)

What is an ACAP and for which applications does it work best?

Kirk Saban: An ACAP is a heterogeneous, hardware adaptable platform that is built from the ground up to be fully software programmable. An ACAP is fundamentally different from any multi-core architecture in that it provides hardware programmability but the developer does not have to understand any of the hardware detail. From a software standpoint, it includes tools, libraries, run-time stacks and everything you’d expect from a modern software-driven product. The tool chain, however, takes into account every type of developer – from hardware developer, to embedded developer, to data scientist and framework developer.

What are the differences to a classic FPGA or SoC?

Saban: A Versal ACAP is significantly different than a regular FPGA or SoC. Zero hardware expertise is required to boot the device. Developers can connect to a host via CCIX or PCIe and get memory-mapped access to all peripherals (e.g. AI engines, DDR memory controllers). The Network-on-Chip is at the heart of what makes this possible. It provides ease-of-use and makes the ACAP inherently SW programmable-available at boot and without any traditional FPGA place-and-route or bit stream. No programmable logic experience is required to get started, but designers can design their own IP or add from the Xilinx ecosystem. With regard to Xilinx’s hardware programmable SoCs (Zynq-7000 and Zynq UltraScale+ SoCs), the Zynq platform partially integrated two out of the three engine types (Scalar Engines and Adaptable Hardware Engines). Versal devices add a third engine type (Intelligent Engines), but more importantly, the ACAP architecture tightly couples them together via the Network-on-Chip (NOC) to enable each engine type to deliver 2-3x the computational efficiency of a single engine architecture, such as a SIMT GPU.

Does this mean, Xilinx will address, besides the classic hardware designers, also application engineers in the future?

Saban: Xilinx has been addressing SW developers with design abstraction tools as well as its HW programmable SoC devices (Zynq-7000 and Zynq UltraScale+) for multiple generations. However, with ACAP, SW programmability is inherently designed into the architecture itself for the entire platform including its HW adaptable engines and peripherals.

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